View AI5412_5069304.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ver1.0
A1 PROs
1
A1 PROs
AI5412
Timing Controller for CCD Monochrome Camera
Description
The AI5412 is a timing and sync one chip controller IC with auto IRIS function for B/W CCD camera systems, which is fabricated in the Hynix 0.8 - MOS process. C
HVDD H1 H2 HVSS RG VSS1 XV2 XV1 XSG1 XV3 XSG2 XV4
Pin Configuration
CKI OSCOUT OSCIN HCOMP MODE5 VDD2 MODE4 MODE3 ESYNC VR/SYNC HPLL EXT
Feature
* EIA / CCIR standards * Auto IRIS function * Supports field / frame accumulation mode * Supports external sync mode * Supports non-interlacing mode * Oscillator frequency : 1212fh (EIA : 19.0699MHz, CCIR : 18.9375MHz) * 48 pin TQFP * Kit with Ai1001S, Ai4402 * Built-in sync signal generation function
AI5412
BLKO SYNC HD VD FLD VSS3 CLP1 CLP2 FL/FR MODE1 SHD SHP
Application
CCD monochrome camera systems.
Absolute Maximum Ratings (Ta = 25 E Vss=0V) ,
Symbol VDD VI Vo TOPR TSTG Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Rating Vss-0.5 to +7.5 Vss-0.5 to VDD+0.5 Vss-0.5 to VDD+0.5 -20 ~ +75 -55 ~ +150 Unit V V V E E
Operating Conditions
Symbol VDD TOPR Parameter Supply Voltage Operating Temperature Rating 5.0 3/4 0.25 -20 ~ +75 Unit V E
1
XSUB ENB IRENB MODE2 IRIN/ED1 Vss2 VDD1 Vreg CVDD SPDNV/ED2 SPUPV/ED0 CVSS
48 PIN TQFP (Top View)
Block Diagram
HD MODE4 MODE3 VD MODE1 FL/FR VDD1 VDD2 VSS2 VSS1 VSS3 MODE5
LPF
40 38 39 34 42 41 33 19 43 6 18 31 44 27 28
HCOMP
EXT ESYNC HPLLVR/SYNC
45
37
46 SYNC SEP
VR1
OSCIN
47 RESET GEN
O/E Field/ Frame
1212fH
OSCOUT
HD1
IRIS/SHUTTER CK GEN.
CKI
48
1/2
1/606
1/525
HVSS
4
H1
2
GATE
13 XSUB
2
H2
3
HVDD
1
Delay
Timing Logic
RG
5
IRIS COUNTER
14 ENB
SHP 25
SHD
SELECTOR
15 IRENB
26
XV1
8 UP/DOWN
ED0
XV2
7
DECODE
ED1 ED2
XV3
10
XV4 12
9
11 36 32 30 29 16
35
24
22
17
SPDNV /ED2
23
IRIN /ED1
21
SPUPV / ED0
20
CVDD Vreg
XSG1 XSG2
CVSS SYNC BLKO FLD CLP1CLP2 MODE2
AI5412
LPF
IRIS SIGNAL
AI5412
Pin Description
NO.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Symbol
HVDD H1 H2 HVSS RG VSS 1 XV2 XV1 XSG1 XV3 XSG2 XV4 XSUB ENB IRENB MODE2 IRIN/ED1 Vss2 VDD 1 Vreg CVDD SPDNV /ED2 SPUPV /ED0 CVSS SHP SHD MODE1
I/O
O O O O O O O O O I I I I*1 I*1 I*1 O O I Power supply (for H1, H2)
Description
H1 clock output for CCD horizontal register drive H2 clock output for CCD horizontal register drive GND(for H1, H2) Reset gate pulse output GND XV2 clock output for CCD vertical register drive XV1 clock output for CCD vertical register drive CCD sensor charge readout pulse output XV3 clock output for CCD vertical register drive CCD sensor charge readout pulse output XV4 clock output for CCD vertical register drive CCD discharge pulse output XSUB pulse output ON/OFF control (with pull-up resistance) Low : XSUB pulse output stop ; High : XSUB pulse output Low : Electronic shutter mode ; High : Auto iris mode (with pull-up resistance) Electronic shutter speed input switchover (with pull-up resistance) Low : serial input ; High : parallel input Iris signal input/shutter speed setting ; clock input in serial mode GND Power supply Bias current supply for comparator Power supply (for comparator) Shutter speed down reference voltage/ Shutter speed setting ; data input in serial mode Shutter speed up reference voltage / Shutter speed setting ; strobe input in serial mode GND(for comparator) Pre charge level sample-and-hold pulse Data sample-and-hold pulse Low : EIA ; High : CCIR (with pull-down resistance)
3
AI5412
NO.
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I*1 I*2 I*3 I*4
Symbol
FL/FR CLP2 CLP1 VSS3 FLD VD HD SYNC BLKO EXT HPLL VR/SYNC ESYNC MODE3 MODE4 VDD2 MODE5 HCOMP OSCIN OSCOUT CKI
I/O
I O O O O O O O O I I I I I I*2 O I*3 O I*4
Description
Field accumulation/frame accumulation, odd field/even field switchover (with pull-down resistance) Pulse output for clamp Pulse output for clamp GND Field identification signal output (High : odd field ; Low : even field) Vertical drive output Horizontal drive output Composite sync output Composite blanking output External sync/internal sync identification signal High : external sync ; Low : internal sync Horizontal drive signal input (with pull-up resistance) Vertical drive signal input/composite sync input (with pull-up resistance) Low : SYNC sync or internal sync ; High : VD/HD sync (with pull-down resistance) Low : interlace mode ; High : non-interlace mode (with pull-down resistance) Line number selection pin (with pull-down resistance) Low : EIA 262H/CCIR 312H ; High : EIA 263H/CCIR 313H Power supply Low : Normal mode ; High : Test mode (with pull-down resistance) Comparator output (H phase comparator) Oscillation (crystal oscillator) inverter input Oscillation (crystal oscillator) inverter output Clock input
Comparator Input Fixed to low level OSCILLATOR Cell Input cell with feedback resistance
4
AI5412
Electrical Characteristics
1) DC Characteristics Item Supply voltage Input voltage Symbol VDD VIH VIL IOH = -2mA IOL = 4mA IOH = -4mA IOL = 8mA IOH = -8mA IOL = 8mA IOH = -12mA IOL = 12mA IOH = -1mA IOL = 1mA VIN = VSS or VDD VIL = 0V VIH = VDD VDD = 5V normal operating state 250K -80 40 28 1M VDD / 2 0.4 2.5M -30 110 VDD - 8 0.4 V V O E E I VDD - 0.8 0.4 VDD - 0.8 0.4 VDD - 0.8 0.4 Conditions (VDD = 5V 3/4 .25V, Topr = -20 to 75 E 0 ) Min 4.75 0.7VDD 0.3VDD Typ 5.0 Max 5.25 Unit V V V V V V V V V
VOH1 Output voltage 1 (All output pins except those below)VOL1 Output voltage 2 (Pins 25, 26) Output voltage 3 (Pin 5, 45) Output voltage 4 (Pins 2, 3) Output voltage 5 (Pin 47) Feedback resistance Pull-up current Pull-down current Current consumption VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 RFB IPU IPD IDD
2) AC Characteristics
SPDNV(ED2) ts2 IRIN(ED1) ts1 SPUPV(ED0) tw0 ts0 th2
Symbol ts2 th2 ts1 tw0 ts0
Item SPDNV (ED2) setup time for IRIN (ED1) rise SPDNV (ED2) hold time for IRIN (ED1) rise IRIN (ED1) setup time for SPUPV (ED0) rise SPUPV (ED0) pulse width SPUPV (ED0) setup time for IRIN (ED1) rise
Min. 20ns 20ns 20ns 20ns 20ns
Max. 50 A -
5
AI5412
Electronic Shutter/Auto IRIS
By setting the ENB pin (Pin 14) high, the XSUB pulse is output for a specific period to activate the electronic shutter and auto iris. 1) Auto Iris (IRENB=high, MODE2=any level) Symbol IRIN/ED1 SPDNV/ED2 SPUPV/ED0 NO. 17 22 23 Iris signal input Shutter speed down reference voltage Shutter speed up reference voltage Function
2) Parallel input electronic shutter (IRENB=low, MODE2=high) Symbol SPDNV/ED2 IRIN/ED1 SPUPV/ED0 NO. 22 17 23 H H H EIA: 1/100 CCIR: 1/120 H H L 1/250 H L H 1/500 Function H L L 1/1000 L H H 1/2000 L H L: 1/5000 L L H L L L
Shutter speed
1/10000 1/100000
3) Serial input electronic shutter (IRENB=low, MODE2=high) Serial input data format SPDNV/ED2
D7 D6 D5 D4 D3 D2 D1 D0
IRIN/ED1
SPUPV/ED0 The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise.
Typical shutter speed
EIA
Load value 00h 4Eh 6Ah 87h 9Ch ACh CAh EDh Shutter speed 1/100000 1/10000 1/5000 1/2000 1/1000 1/500 1/250 1/100 Load value 00h 4Ah 65h 82h 97h A7h C5h E1h
CCIR
Shutter speed 1/80000 1/10000 1/5000 1/2000 1/1000 1/500 1/250 1/120
6
AI5412
External Synchronization
1) External/internal sync selection External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. VR/SYNC pin : SYNC signal VR/SYNC pin : VD signal HPLL pin : Open HPLL pin : HD signal ESYNC pin : Open ESYNC pin : VDD High External sync High External sync VR/SYNC pin : Open HPLL pin : Open ESYNC pin : Open Low Internal sync
Input pattern EXT pin output Sync state
Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization.
2) Modes for external synchronization Mode
Interlace
Field accumulation
Frame accumulation
O X
(Cannot be accomplished since interlace operation is the prior condition)
O X
(Cannot be accomplished since interlace operation is the prior condition)
SYNC
synchronization Non-interlace Interlace
O O
O X
(Not practically applicable since the sensitivity is halved)
VD/HD
synchronization Non-interlace
3) Reset operation SYNC synchronization The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset is performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse. For CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. VD/HD synchronization V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse supplied externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.)
7
AI5412
Mode Control
Symbol ENB IRENB MODE2 IRIN/ED1 SPDNV/ED2 SPUPV/ED0 MODE1 FL/FR NO. 14 15 16 17 22 23 27 28 I/O I I I I I I I I Field accumulation HPLL 38 I Frame accumulation Low XSUB stop Electronic shutter Serial input High XSUB output Auto iris Parallel input Valid only when ENB is high. Valid only when ENB is high and IRENB is low Remarks
Auto iris control signal input pin (IRENB = high) Shutter speed setting pin (IRENB = low) EIA Odd field CCIR Even field
Valid only when ENB is high.
Valid only when MODE3 is high and EXT is low. Valid in all other modes.
VR/SYNC
39
I
Internal sync : HPLL (open) VR/SYNC (open) SYNC sync : HPLL (open) VR/SYNC (SYNC input) VD/HD sync : HPLL (HD input) VR/SYNC (VD input) SYNC sync Internal sync Interlace EIA : 262H CCIR : 312H VD/HD sync Non-interlace EIA : 263H CCIR : 313H Valid only when EXT is low. Valid only when EXT is low and MODE 3 is high. Switchover between internal and external sync is automatically identified by input state at Pins 38, 39 and 40.
ESYNC MODE3 MODE4
40 41 42
I I I
EXT
37
O
Internal sync
External sync
8
AI5412
Mode Tables
1) Internal sync mode
HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : Open ESYNC pin (Pin 40) : Open
Interlace Field readout O O O Frame readout O O O
XSUB pulse OFF*1 Electronic shutter ON Auto iris ON
Non-interlace Odd field *2 Even field *2 Field Frame Field Frame readout readout readout readout O X O X O O X X O O X X
O : Can be used. X : Cannot be used.
*1 EIA for 1/60 s accumulation ; CCIR for 1/50 s accumulation *2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR.
2) SYNC sync (external sync) mode
HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : SYNC input ESYNC pin (Pin 40) : Open
Interlace Field readout O O O Frame readout O O O
XSUB pulse OFF*1 Electronic shutter ON Auto iris ON
Non-interlace Odd field *2 Even field *2 Field Frame Field Frame readout readout readout readout X X X X X X X X X X X X
O : Can be used. X : Cannot be used.
*1 EIA for 1/60 s accumulation ; CCIR for 1/50 s accumulation *2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR.
3) VD/HD sync (external sync ) mode
HPLL pin (Pin 38) : HD input VR/SYNC pin (Pin 39) : VD input ESYNC pin (Pin 40) : VDD (power supply)
XSUB pulse OFF*1 Serial input electronic shutter ON Parallel input electronic shutter ON Auto iris ON
VD input with normal cycle VD input with longer cycle than Non-interlace Interlace normal Interlace 2 2 Odd field * Even field * Field Frame Field Frame Field Frame Field Frame readout readout readout readout readout readout readout readout O O O X O X O X O O O O O O O a O X X X O a O X X X X X X X X X
*1 EIA for 1/60 s accumulation ; CCIR for 1/50 s accumulation *2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR.
O : Can be used. a The shutter speed may change from : its value in the interlace mode. X : Cannot be used.
Note ) Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than normal are input to the VR/SYNC pin.
9
AI5412
( Timing Chart 1 )
EIA/CCIR
52.4ns(EIA) 52.8ns(CCIR)
High-Speed phase
CK
H1
26.2ns(EIA) 26.4ns(CCIR)
RG
CCD OUT
SHP
SHD
10
(Timing Chart 2) Horizontal effective period
EIA
1/2H 1.468 s(14CK) 1CK=104.87ns
1.468 s(14CK)
HD
6.187 s (59CK)
BLKO
10.9 s (104CK)
HSYNC
4.72 s (45CK)
4.72 s (45CK)
EQ
2.3 s (22CK)
VSYNC
VD
11
1/2H 1.478 s(14CK) 4.75 s (45CK)
FLD
CCIR
1.478 s(14CK)
1CK=105.6ns
HD
6.23 s (59CK)
BLKO
12.04 s (114CK)
HSYNC
4.75 s (45CK)
EQ
2.3 s (22CK)
VSYNC
VD
AI5412
FLD
( Timing Chart 3 ) Charge Readout Timing
A. Field accumulation
E:EIA 1CK=104.87ns C:CCIR 1CK=105.6ns (24CK) E:2.51 S C:2.53 S
HD
XSG1
XSG2
(366CK) E:38.38 S C:38.65 S (15CK) E:1.57 S C:1.58 S (12CK) E:1.26 S C:1.27 S
ODD
XV1
12
(3CK) E:0.315 S C:0.317 S (19CK) E:1.99 S C:2.0 S
XV2
XV3
XV4
EVEN
XV1
XV2
XV3
AI5412
XV4
B. Frame accumulation
E:EIA 1CK=104.87ns C:CCIR 1CK=105.6ns
(24CK) E:2.51 S E:2.53 S
HD
XSG1
XSG2
(378CK) E:39.64 S C:39.92 S
ODD
XV1
XV2
13
(3CK) E:0.315 S C:0.317 S
XV3
XV4
EVEN
XV1
XV2
XV3
AI5412
XV4
( Timing Chart 4 )
( MCK=CKI/2 ) 59 10 60 70 80 90 100 20 30 40 50 104
A. H direction, EIA
HD
MCK
H1
H2
RG
SHP
SHD
23 80 32 44 62 56 38 55 14 14 36 14 14 59 68 73 26 50 94 103
CLP1
7
CLP2
14
XV1
49
XV2
XV3
XV4
XSUB
HSYNC
EQ
VSYNC
FLD
AI5412
VD
B. H direction, CCIR
( MCK=CKI/2 ) 59 20 40 60 90 30 50 70 80 100 114
HD
10
MCK
H1
H2
RG
SHP
SHD
23 84 37 49 31 43 60 14 14 14 14 36 59 61 73 77 67 55 98 107
CLP1
7
CLP2
15
XV1
XV2
XV3
XV4
XSUB
HSYNC
EQ
VSYNC
FLD
AI5412
VD
( Timing Chart 5) Low - Speed Phase
FIELD. E 9H FIELD. O
A. V direction, EIA
HD VD SYNC BLKO
20H
FLD XSG1 XSG2 XV1 XV2 XV3 XV4 CCD OUT
491 493 492 1 2 3
16
FIELD. O 9H FIELD. E 20H 492 493
CLP1 CLP2
HD VD SYNC BLKO FLD XSG1 XSG2
1 2
3 4
XV1 XV2 XV3 XV4 CCD OUT CLP1 CLP2
AI5412
B. V direction, CCIR
FIELD. E 7.5H FIELD. O
25H 14.5H
581 582 583 1
2 3
17
FIELD. E 7.5H 25H 14H 582 583
HD VD SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 XV4 CCD OUT CLP1 CLP2
HD VD SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 XV4 CCD OUT CLP1 CLP2
FIELD. O
AI5412
( Timing Chart 6 )
External Synchronization reset Operation
FIELD. O 9H
FIELD. E
EIA
HD
VD
SYNC
HD1
VR1
VDR FIELD. E 9H
FIELD. O
HD
VD
SYNC
HD1
VR1
18
FIELD. O 7.5H
VDR
HD
FIELD. E
CCIR
VD
SYNC
HD1
VR1
VDR FIELD. E 7.5H
FIELD. O
HD
VD
SYNC
HD1
VR1
AI5412
VDR
2.2K 2.2K 47p 2.2K 271p 100 220p 100
2.2K
Application Circuit
47p
36 35 34 33 32 31 30 29 28 27 26 25
24 21 25 30 4
29
37 23 22
6.8 i/6.3V 50K
24
50K
20
38 21 20
SYNC IN
39
40
0.1 i
41
Signal Processor
150K IMX1 270K
19
19 18
0.1 i
42
27
AI5412
17 16 15
10K 0.15i 3.9K
0.1 i 36K 6.8 i /6.3V
43
6.8 i /6.3V
44
IRIS
45 14 13 3 5 7 8 4 6 9 10 11 12
46
47
22p
22p
48
0.1 i
1
2
19.0699MHz(EIA) or 18.9375MHz(CCIR)
VIDEO OUT
0.1 i
6.8 i/6.3V
33 VSUB ADJ
33
RG ADJ
CCD(250/290K pixels
Vertical Driver
CCD OUT
AI5412
AI5412
Package Outline
UNIT : mm 48pin TQFP(PLASTIC)
0.05 0.10 C
0.10 -C# 0.220.05 0.5BSC
v 0.20 C A-B D
DATUM PLANE 9.00BSC *7.0BSC -A-B-
-D(3.5) *7.0BSC 9.00BSC
DD
(3.5)
0.20 H A-B D 0.20 C A-B D
0.2MIN
0.MIN -H(0.6375)
1.400.05
. RO
0-7
0.100.05
0.60.15 1.00REF GAUGE PLANE
DETAILS of " A "
Note ) 1. DIMENSION * MARK DOES NOT INCLUDE MOLD FLASH 2. DIMENSION # MARK DOES NOT INCLUDE DAMBAR PROTRUSION 3.UNSPECIFIED IS ACCORDING TO JEDEC MO-136, VARIATION "BE"
0.09-0.2 0 0.25
(0.6375)
20 -0. 08
20
8-121
"A"
D
1.50MAX
.

▲Up To Search▲

Price & Availability of AI5412

	To Download AI5412 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .